Among the types of semiconductor memory devices that read data out in pages and/or bursts are flash memories. A flash memory is a kind of read-only-memory (ROM) that is often referred to as a flash electrically erasable programmable ROM (EEPROM). A flash EEPROM is a nonvolatile semiconductor device, the contents of which can be electrically erased or written. A conventional configuration for this type of semiconductor memory device will be described below with reference to FIG. 11.
FIG. 11 is a block diagram showing the configuration of a conventional semiconductor memory device. Note that FIG. 11 illustrates a configuration for reading out data. To avoid unduly cluttering the view, sections utilized in writing data, and a mode control circuit for placing the semiconductor memory device in various operating modes, and the like, are omitted.
As shown in FIG. 11, a conventional semiconductor memory device is configured to include a memory cell array 101 composed of a number of memory cells in which data is stored, a sense amplifier 102 for reading out data stored in memory cell array 101, a page buffer 103 for temporarily holding the data read out from the memory cell array 101, an output buffer 104 for outputting the read-out data to the outside of the device, a number of input buffers 105 for receiving an address signal from outside the device, and a number of address generating circuits 106 that each generate a control signal according to which data is to be output from the page buffer 103 based on the mode. Such a mode can be a page mode or burst mode.
In the conventional semiconductor memory device of FIG. 11, the number of sense amplifiers 102 provided agrees with a given page length or burst length to enable a collective read-out of data for the memory cell array 101 corresponding to such lengths. Data read out from a memory cell array 101 is held in the page buffer 103. Such data is then output at a page length or burst length synchronously with control signals IA0 to IA2 generated in address generating circuit 106.
It is noted that the conventional semiconductor memory device shown in FIG. 11 is configured to read out, for example, the data of two words in units of eight data at a maximum (the page length and the burst length equals eight). Thus, in the configuration of FIG. 11, data can be read out from the memory cell region 101 using upper bits of an address signal (e.g., A3 to A22: hereinafter referred to as the “normal” address). Then, the data for the page length or burst length is output in a predetermined order from the page buffer 103 using the lower bits of the address signal (e.g., A0 to A2: hereinafter referred to as the “page” address). It is noted that a circuit for selecting the above-mentioned cell region is omitted in FIG. 11.
A conventional address generating circuit 106 can have a burst address counter 107 and an address selecting circuit 108. The burst address counters 107 are incremented synchronously according to a predetermined clock, and provide internal address signals IA2_B, IA1_B and IA0_B. In the page mode, address selecting circuit 108 outputs internal address signals IA2_A, IA1_A and IA0_A, provided from input buffers 105, as control signals IA2 to IA0, respectively. In the burst mode, address selecting circuit 108 outputs internal address signals IA2_B, IA1_B and IA0_B, provided from burst address counters 107, as control signals IA2 to IA0, respectively.
With such a configuration, page addresses from the outside of the device are provided as control signals IA2 to IA0 in the page mode, and a count result from burst address counters 107 is provided as control signals IA2 to IA0 in the burst mode. The page buffer 103 decodes control signals IA2 to IA0 supplied from address generating circuit 106 to output data DQ of addresses corresponding to a decode result.
In the conventional semiconductor memory device described above, the amount of data collectively read out from the memory cell array to the page buffer is equal to a page length or a burst length. As a result, there is a need to include a number of sense amplifiers corresponding to a maximum page length or maximum burst length. Still further, such a configuration must allow for necessary access combinations that may be required. In particular, while it may be required that data be read from a memory cell array according to a one lower address order (e.g., 000, 001, 010, . . . 111), data may also have to output in some other arbitrary order.
In the above arrangement, the sense amplifier 102 reproduces data stored in the memory cell array according to all bits that are required for a read operation. Thus, in the case where data of two words (32-bits) are read out in units of 8, 256 (8×32) sense amplifiers are required.
In a conventional semiconductor memory device, such as a flash memory, a sense amplifier is provided with a reference cell for judging whether each bit of data read is a “1” or “0”. Further, a circuit is also provided for supplying the reference cell with a predetermined current. Still further, in recent semiconductor memory devices, memory cells can store multi-valued data values, instead of only binary data of “1” or “0”. In such an arrangement, a reference cell and circuits for supplying current to the reference cell are increased in scale. As a result, circuit size continues to increase as devices are scaled to store more data.
Due to the above, a problem arises in that a large layout area is required for sense amplifiers, resulting in increased chip size. This works against the goal of limiting chip sizes by requiring limited memory cell array sizes. Moreover, as the number of sense amplifiers is increased, the power consumption of the overall semiconductor memory device increases.
In light of the above, it would be desirable to address the above problems present in conventional approaches. In particular, it would be desirable to provide a semiconductor memory device having a reduced number of sense amplifiers to thereby suppress increases in chip size and reduce power consumption. At the same time, it would desirable that such a semiconductor memory device be capable of providing page mode and burst mode read access.